1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of interconnect lines arranged in parallel with each other, for example, word lines of a memory cell array, and a method of producing a semiconductor device shortening the distance between interconnect lines to the maximum extent.
2. Description of the Related Art
The word lines of for example a flash electrically erasable and programmable read only memory (flash EEPROM) or other nonvolatile memory device serve also as gate electrodes of the memory transistors and are arranged extending in a row direction of the memory cell array. These word lines are repeatedly arranged at predetermined intervals in the column direction. When bit lines are formed by patterning a metal, polycrystalline silicon, etc., the bit lines are also arranged in parallel to each other at predetermined intervals.
As other interconnect lines arranged in this way, there are word lines or bit lines of other memories (other read only memories (ROMs) or random access memories (RAMs)) gate lines of gate arrays, and numerous other interconnect lines.
When patterning such interconnect lines, first a conductive material is formed, then a resist is coated on the conductive material and patterns on a reticle or other photomask are transferred to the resist. Using the resist to which the patterns have been transferred as a mask, the conductive material is then etched and patterned.
Alternatively, a material with a stronger resistance to etching is interposed between the conductive material and resist, then the patterns of the resist are transferred once to the layer of the material with the strong etching resistance. Next, the layer of the material with the strong etching resistance to which the patterns are transferred is used as a mask to etch and pattern the conductive material.
Summarizing the problems to be solved by the invention, with these methods, it is not possible to pattern the material at under the resolution limit of photolithography, which is dependent on the wavelength of the light used.
As a method for patterning a material at under the resolution limit of photolithography, the so-called “phase shift method” is known.
There is however a limit to the reduction of the distance between interconnect lines by this method. It is not possible to reduce the distance between interconnect lines to an extreme extent.
Therefore, in semiconductor memories of the related art, for example, the general practice has been to form the word lines in parallel stripes spaced apart from each other by the same extent as the widths as the word lines. This wasted space in the column direction and has been one factor obstructing the reduction of the bit cost.
The problem of the limit to reduction of area due to the interconnect line pitch is basically found in all semiconductor devices with numerous fine repeating interconnect line patterns such as other interconnect lines of the memory devices and interconnect lines of gate arrays.